Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others.
Flash memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Uses for flash memory include memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among other electronic devices. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line, which is commonly referred to in the art as a “word line”. However each memory cell is not directly coupled to a data line (which is commonly referred to as a digit line, e.g., a bit line, in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a data line, where the memory cells commonly coupled to a particular data line are referred to as a “column”.
Memory cells in a NAND array architecture can be programmed to a target, e.g., desired, state. For example, electric charge can be placed on or removed from a charge storage structure of a memory cell to put the cell into one of a number of program states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also store more than two states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells can be referred to as multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. For example, a cell capable of representing four digits can have sixteen program states.
Capacitive coupling can exist between charge storage structures, e.g., floating gates, of flash memory cells. As an example, the threshold voltage (Vt) of a cell programmed to a target state can change, e.g., increase, due to capacitive coupling associated with floating gates of adjacent cells. The amount of Vt change, e.g., Vt shift, associated with a cell programmed to a target state due to capacitive coupling can depend on the Vt of one or more adjacent cells. For instance, adjacent cells programmed to a higher program state, e.g., a state associated with a higher Vt, may have a greater effect on the Vt of the target cell than adjacent cells programmed to a lower program state, e.g., a state associated with a lower Vt. In some instances, the Vt shift of a target cell, e.g., due to programming of an adjacent cell, can lead to erroneous sensing of the target cell. For instance, the Vt shift may be sufficient such that a sensing operation performed on the target cell results in a determined sensed state other than the target state of the target cell.
One approach to compensating, e.g., tracking, for changes in the Vt of a memory cell, e.g., due to capacitive coupling, can include using a reference cell during a sensing, e.g., read, operation on the memory cell. However, the use of reference cells can increase the area of the memory array, decrease the quantity of memory cells in the array, and/or increase the amount of circuitry associated with the memory device.